1. Field of the Invention
The present invention generally relates to the generation and synchronization of clock signals in a system. More particularly, the present invention relates to delay locked loop or a phase locked loop implemented with digital circuitry. Still more particularly, the present invention relates to a digitally-designed delay locked loop that produces a linear delay line gain.
2. Background of the Invention
Delay locked loops (DLLs) and phase locked loops (PLLs) are commonly used in electrical system to synchronize a signal with a clock signal. For example, in a synchronous circuit, a DLL may be used to synchronize a data output signal with a clock signal output. Thus, one typical implementation of a DLL is to delay the transmission of the data output signal to coincide with an edge of a clock signal. The ability of the receiving device to properly interpret the data output signal depends, at least in part, on the ability of the DLL to make the data output available within tightly controlled time periods relative to the clock signal. If the data output signal is not delayed for a sufficient time interval, the data output signal may be delivered prematurely, prior to the time when the receiving device is expecting the data (based on predefined timing protocols). This can also lead to the receiving device misinterpreting the data output signal. The ability of the DLL to operate within very tightly defined tolerances is critical to successful operation of many electrical systems.
Traditionally, delay locked loops have been implemented as analog circuits, despite the fact that many DLLs are used in digital circuit designs, such as computer systems and other microprocessor-based designs. Analog circuits have been selected because of the familiarity of system designers with analog designs, the ability to infinitely adjust the delay loop, and the simplicity of the implementation. Although less common than analog designs, digital DLLs offer the potential for certain improvements over existing analog designs. In particular, digital DLLs have the capability of improving run time, providing programmable control, scaling more readily to new technology processes, being less reliant on the characterization of discrete circuit elements such as resistors and capacitors, and providing greater noise immunity. Despite these potential advantages, system designers have proven hesitant to use digital DLLs due to performance concerns. One specific concern is whether tracking is well-behaved and monotonic. If the delay times through different delay lines has non-linear anomalies, the effects of jitter (which is the variation of the delay through the delay lines caused by noise) may be unacceptable.
In conventional digital DLLs and/or PLLs, a phase detector increments or decrements a binary counter to indicate the difference (or the misalignment) in phase between a synchronizing signal and a clock signal. See e.g., Jim Dunning, “An All-Digital Phase-Locked Loop with 50-Cycle Lock Time Suitable for High-Performance Microprocessors,” IEEE Journal of Solid-State Circuits, Vol. 30, No. 4 (April 1995). The phase comparator thus indicates whether the feedback signal is before or after the reference signal, and transmits a signal to the binary counter to speed up or slow down the feedback signal. The digital output of the binary counter then is used to control the amount of delay to be added to the synchronizing signal to align it with the clock signal. One typical technique is to couple the output signal from the binary counter to a digital-to-analog converter, thus producing an analog signal corresponding to the desired delay period. The analog signal then is used to control the delay line. Alternatively, the binary counter may be coupled directly to delay lines, with each output terminal of the binary counter connected to (or enabling) a delay line. Thus, for example, multiple delay lines may be constructed with a different number of inverters, and the binary counter output bits may then be used to select which of the delay lines is used to delay the data output signal. Alternatively, parallel capacitor loads may be used instead of inverter delay elements.
While both of these approaches have met with some limited success, neither approach has been effective in eliminating concerns about the performance of digital delay locked loops. With respect to the first approach, the use of a digital-to-analog converter introduces analog issues into the design, thereby eliminating many of the advantages of a purely digital design. The second approach, while achieving some of the advantages of a purely digital design, requires very careful design and characterization of the delay lines. One particular concern is that the phase error will depend on the counter value, if the delay line gain from line-to-line is not monotonic. This effect is particularly of concern as the counter changes multiple output bits. For example, as the counter increments from a delay value of 31 to 32, five “1s” must change to a single “1” followed by five “0s” (011111 transitions to 100000). Thus, before the transition, five legs of the delay element are enabled, and afterwards, a single delay element leg is enabled, which must exceed the combined delay effect of the other five delay element legs. It can be extremely difficult to design the delay element legs to insure a monotonic or constant time delay value for each count of the counter. Unless carefully designed, the combination of delay element legs may exhibit some degree of non-linearity, which reduces the ability of the DLL to synchronize to the master clock with any degree of precision.
It would be advantageous if a digital DLL could be developed with enhanced performance. In particular, it would be desirable if a DLL was designed that exhibited monotonic or constant delay gain in response to an increase in the binary counter value. The ability to achieve a linear tracking of the binary counter value to the amount of delay introduced, would greatly enhance the performance of digital DLLs, and would lead to a greater acceptance of such designs.